PIC16C63A-20/SS【PDF 43/184 页】IC MCU OTP 4KX14 PWM 28SSOP

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137

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

20.3.2

Entering Serial Programming Mode

The following algorithm puts the device in Serial Programming Mode:

Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.

Apply XIN clock within T

POR_RESET + 32(TSCLK) if an external clock is available.

Wait for T

POR_RESET.

Reset the TAP controller clocking 5 TCK pulses with TMS set.

Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.

Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-Test-Idle state.

Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.

Note:

After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (> 32

kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher

frequency on XIN speeds up the programmer handshake.

20.3.3

Read/Write Handshake

The read/write handshake is done by carrying out read/write operations on two registers of the device that are

accessible through the JTAG:

Debug Comms Control Register: DCCR

Debug Comms Data Register: DCDR

Test

TST

Test Mode Select

Input

High

Must be connected to VDDIO.

PGMEN0

Test Mode Select

Input

High

Must be connected to VDDIO

PGMEN1

Test Mode Select

Input

High

Must be connected to VDDIO

PGMEN2

Test Mode Select

Input

Low

Must be connected to GND

JTAG

TCK

JTAG TCK

Input

Pulled-up input at reset

TDI

JTAG Test Data In

Input

Pulled-up input at reset

TDO

JTAG Test Data Out

Output

TMS

JTAG Test Mode Select

Input

Pulled-up input at reset

Table 20-20. Signal Description List (Continued)

Signal Name

Function

Type

Active

Level

Comments

Table 20-21. Reset TAP Controller and Go to Select-DR-Scan

TDI

TMS

TAP Controller State

Test-Logic Reset

Run-Test/Idle

Select-DR-Scan

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